1. Field of the Invention
The present invention relates to a memory circuit.
2. Description of the Prior Art
In the prior art, a sense amplifier is used in order to amplify a fine read signal derived from an internal storage apparatus or external storage apparatus (memory) of an electronic calculator to a voltage level of a logic circuit.
In the case of a prior art memory circuit of, for example, a static type, its memory matrix is formed of a plurality of memory cells which are connected to a word line and to a pair of bit lines. Each memory cell includes a flip-flop circuit formed of a load resistor and an MOS (metal oxide semiconductor) transistor and stores an information in response to on and off of a current. The pair of bit lines are connected through a pair of N-channel MOS transistors to a power source terminal and further connected through a selection transistor formed of another pair of N-channel MOS transistors to a write circuit.
The write circuit includes a pair of N-channel MOS transistors which are controlled by an inverted write enable control signal and another pair of N-channel MOS transistors which are controlled by a write enable control signal. They are connected with a data line and an inverted data line and connected between the power source terminal and a data input terminal.
When the inverted write enable control signal is high in level, a data is read out from the memory and then delivered through a sense amplifier circuit formed of a differential amplifier circuit connected to the write circuit. Whereas, when the write enable control signal is high in level, a data supplied to the data input terminal is stored in the memory. However, in the above mentioned write mode, when a data "0" is written in the memory, the level at the output terminal of an inverter connected to the data input terminal becomes an earth potential so that a write current is flowed from the power source terminal through the inverted bit line and the inverted data line.
On the other hand, a MOS transistor of a constant current source in the differential amplifier circuit of the read circuit is supplied with a chip select signal so that regardless of the write mode and the read mode, if the chip select signal is high in level, the operation current is flowed to the differential amplifier circuit and thus the constant power is consumed. Accordingly, the power cosumption of the memory becomes more larger in the write mode so that the write current and the operation current of the differential amplifier circuit become as large as 1 M and 3 mA respectively although the above mentioned values are fluctuated on the basis of the operation speed of the memory.